Goals for integrated circuit design include progressively scaling the design to achieve smaller feature sizes, and using faster clock frequencies beyond 1 GHz. Problems encountered in achieving these goals include the increasing voltage droop and the inductive noise of the active switching nodes, and further include the increasing power supply oscillations and the resulting noise that is generated and transmitted across the chip.
These problems are addressed by incorporating on-chip decoupling capacitors into the integrated circuit design. On-chip decoupling capacitors provide a uniform power supply voltage supply (VDD) to fast switching nodes and offset the voltage droops caused by resistive and inductive losses in the integrated circuit load. As such, as will be described in more detail below, on-chip decoupling capacitors reduce ΔI and ΔV noises in CMOS circuits.
The resonance impedance (ZRES) of the chip is directly proportional to the inductive component and inversely proportional to the chip RC as represented by the following equation:
                Z      RES            ∝            L                        (                                    R              C                        +                          R              DC                                )                +                  (                                    C              C                        +                          C              DC                                )                      .  The values RC and CC represent the resistance and capacitance of the chip, respectively. The values RDC and CDC represent the resistance and capacitance of the decoupling capacitor, respectively. The resonance frequency (FRES) of the chip is inversely proportional to the square root of L+C as represented by the following equation:
                F      RES            ∝            1                        L          +                      (                                          C                C                            +                              C                DC                                      )                                .  The VDD oscillation and the VDD noise can be suppressed by a significant and simultaneous lowering of both ZRES and FRES.
Conventionally, on-chip decoupling capacitors are fabricated using silicon dioxide (SiO2) capacitance in the form of Metal Oxide Silicon (MOS) capacitors. SiO2 has a low dielectric constant (K≈3.9), i.e. a low capacitance per unit area, such that a relatively large amount of silicon area is required for a given capacitance. Thus, the use of SiO2 adversely affects both density and yield.
Conventional capacitors that are constructed with defect-free silicon dioxide are characterized as “loss-less” capacitors because, when used as decoupling capacitors, they provide added capacitance to the chip but provide no resistive component. As such, a separate series resistor is often fabricated with conventional on-chip decoupling capacitors to reduce ZRES.
It is desirable for a decoupling capacitor to have a controlled and large value of capacitance per unit area, i.e. a high K value, to provide an effective capacitance (CDC) in a relatively small area and to have a built-in controlled resistance (RDC) in order to control the resonance impedance and the resonance frequency. Thus, it is desirable to provide controlled and effective “lossy” decoupling capacitor structures and processes that provide a significantly larger value of capacitance per unit area and overcome high frequency design challenges.
One known on-chip decoupling capacitor that has an adjustable ZRES includes two thin layers of SiO2 between a silicon substrate and a doped polysilicon plate, and further includes a thin layer of “injector” quality silicon-rich-nitride (SRN), which is described below, between the two thin layers of SiO2. For example, a known capacitive device includes an insulating layer of SiO2 having a thickness of 25 Å, an SRN layer having a thickness of 50 to 85 Å, and an SiO2 layer having a thickness of 15 Å. A known process sequence for forming this device includes growing 25 Å of SiO2 on a silicon substrate. SRN is deposited to a thickness of 50-85 Å using Low Pressure Chemical Vapor Deposition (LPCVD) or Plasma Enhanced Chemical Vapor Deposition (PECVD). A Rapid Thermal Anneal (RTA) in O2 ambient is performed, and the top oxide and SRN layers are patterned and etched such that the SRN layer is left only over N-well regions in the silicon substrate for subsequent capacitor formation. The bottom oxide is removed to form field effect transistor (FET) gate regions and gate oxide is grown. Polysilicon is deposited, doped and patterned to simultaneously form FET gates and the top plate of the capacitor device.
The above-described known on-chip decoupling capacitor is limited by the scalability of the SiO2 film thickness, and requires a large silicon area to provide a significant value of capacitance due to the inherently low dielectric constant of SiO2. Furthermore, even though superior to conventional oxide, this known on-chip decoupling capacitor has a defect, yield and reliability impact similar to thin SiO2 gate films.
Therefore, there is a need in the art to provide a system and method that overcomes these problems. The present invention overcomes the above limits of scalability, yield and reliability and provides design solutions for significantly higher frequency ranges, lower voltages, and smaller feature sizes for future generations of integrated circuit design.